1. Field of the Invention
The present invention relates to the field of CMOS process techniques, and more particularly, it relates to a semiconductor device and a manufacturing method thereof.
2. Description of the Related Art
In the advanced CMOS (complementary metal oxide semiconductor) technology, an eSiGe (Embedded SiGe) process is proposed to increase the compressive stress of channel area of a PMOS (P-channel metal-oxide-semiconductor field-effect transistor) device as well as to enhance the carrier mobility thereof, in which, an embedded SiGe is used for forming a source region or a drain region, so as to apply a stress on the channel area, thereby improving the performance of the PMOS. The eSiGe process faces many challenges, and one important factor that should be considered is the selectivity of SiGe (silicon germanium) epitaxial growth. Generally, it is necessary to grow SiGe or SiGe:B (SiGe with in-situ-doped B) in a PMOS recess region, and the functionality of a semiconductor device will be affected if SiGe or SiGe:B grows on undesired regions.
In the prior art, there are two eSiGe integrating process flows. One process flow is referred to as a DSW (disposable sidewall) process flow, which generally comprises forming isolation region (e.g. STI), forming a gate oxide, forming a gate, forming a disposable sidewall, forming a S/D (source/drain) recess and SiGe SEG (selective epitaxial growth), removing the disposable sidewall, forming an offset spacer, performing halo and extension region (Halo & Ext.) ion implantations, forming a SW (sidewall), and performing RTA (rapid thermal annealing), such as millisecond anneal (m-sec anneal). Since eSiGe-S/D is formed prior to the formation of the offset spacer, this process flow is also referred to as “SiGe-first” process flow. The other process flow is referred to as “SiGe-last” process flow, which roughly comprises forming isolation, forming a gate oxide, forming a gate, forming an offset spacer, performing halo and extension region ion implantations, forming a sidewall SW, forming a S/D recess and SiGe SEG, and performing RTA, or the like.
FIGS. 1A-1F schematically show the sectional views of each stage of the SiGe-last process flow in the prior art.
As shown in FIG. 1A, a spacer material SiN 150 is deposited. A Si substrate 100 comprises a STI 110, an NMOS (n-channel metal-oxide-semiconductor field effect transistor) region 120 for an NMOS device, and a PMOS region 130 for a PMOS device, wherein gates 140 are formed on the NMOS region 120 and the PMOS region 130, an oxidation layer 160 is also formed thereon, and SiN is deposited on the oxidation layer 160 as the spacer material.
As shown in FIG. 1B, a sidewall spacer 150 is formed by etching, and the spacer material on other positions of the NMOS region and the PMOS region is removed.
As shown in FIG. 1C, the NMOS region is covered with a photo-resist 170.
As shown in FIG. 1D, a PMOS S/D recess 180 is formed by a dry etching or a combination of a dry etching and a wet etching.
As shown in FIG. 1E, the photo-resist 170 is removed.
As shown in FIG. 1F, SiGe epitaxial growth is performed.
However, since the oxide 160 on the NMOS region 120 is relatively thin, SiGe may grow on the NMOS region, which consequently affects the performance of a semiconductor device.
In the SiGe process flow of the prior art, including SiGe-first process flow and SiGe-last process flow, for example, after a wet cleaning process and a SiGe pre-baking process, the thin oxidation layer that covers the NMOS S/D region may fail to protect the NMOS region such that SiGe also grows on the NMOS region. Thus, the growth of SiGe on the NMOS region becomes a major concern.